1. Field of the Invention
This invention relates to an electrically rewritable nonvolatile semiconductor storage device, particularly one called flash memory improved in element separability between bit lines, and to its manufacturing method.
2. Description of the Prior Art
NAND cell-type EEPROM is known as one of nonvolatile semiconductor storage devices enabling high integration, i.e., flash memory devices. It comprises a plurality of memory transistors connected in series for respective adjacent ones to share each source/drain region in each unit, and each unit forms a NAND memory cell. Memory transistors, in general, have a FET-MOS structure stacking a floating gate for accumulating an electric charge and a control gate. The drain side of a NAND memory cell is connected to a bit line through a selection gate, and its source side is connected to a source line through a selection gate. Control gates of NAND memory cells are aligned successively in the row directions to form word lines.
Data writing operation of NAND cell-type EEPROM follows the process explained below. A write potential (18 V, for example) is applied to the control gate of a selected memory transistor whereas an intermediate potential (about 8 V, for example) is applied to control gates of the other non-selected memory transistors. 0 V or the source voltage (about 3.3 V, for example), depending on data, is applied to bit lines. When 0 V is applied to a bit line, the potential is transmitted to the drain region of the selected memory transistor via non-selected memory transistors. Then, electrons are injected from the drain region into the floating gate by F-N tunneling, and the threshold value of the selected memory transistor is shifted forward. This state is determined as 0, for example. When the source voltage (about 3.3 V, for example) is applied to the bit line, selection gates are cut off, and the potential at the channel portion of the selected memory transistor is raised by the writing potential applied to the control gate of the selected memory transistor and the intermediate potential applied to control gates of non-selected memory transistors. Therefore, electron injection does not occur, and the threshold value remains negative. This state is determined 1, for example. This is the writing operation.
When the element separation width is narrowed along with progressive micro-miniaturization, the resistivity to voltage at the bit line contacts where bit lines contact the drain regions of selection gates arises as a problem. That is, it becomes difficult to maintain the resistivity to a punch-through voltage between neighboring bit line contacts with a certain margin. If a NAND memory cell for writing 0 and another NAND memory cell for writing 1 are adjacent to each other, and the resistivity to a punch-through voltage between their bit contacts is insufficient, the potential of the source voltage applied for writing 1 leaks to the adjacent bit line contact. Therefore, the drain of the NAND memory cell having the memory transistor which should write 1 cannot rise to the source voltage (about 3.3 V, for example), and results in writing 0. That is, erroneous writing occurs. Therefore, it is important to provide a sufficient margin, taking differences in resistivity to the punch-through voltage among bit line contacts into account.
Element isolation between adjacent bit line contacts so far relied on field implanted regions formed by impurity ions implanted upon making a field oxide film. Therefore, in a structure with a narrow element separation width, the margin against punch-through was very small. In a structure with an increased dose amount of impurity ions implanted upon making the field implanted region for the purpose of increasing the punch-through margin, other problems occurred, such as diffusion of excessive impurities into the channel region, and an increase in capacitance between the channel region and the field implanted region. Diffusion of excessive impurities into the channel region reduces the cell current, and hence decreases the margin for read-out operation. Moreover, an increase in capacitance between the channel region and the field region makes it difficult for bit lines of memory transistors not for writing during writing operation to rise, and makes error writing to occur more often. These reasons were the bars against the approach relying on increasing the dose amount of impurity ions implanted into the field implanted region upon making the field oxide film.
NAND cell-type EEPROM needs at least the source voltage (about 3.3 V, for example) as the resistivity to punch-through voltage between bit line contacts. Moreover, it needed at least the writing voltage (about 18 V, for example) as the resistivity to field inversion voltage of memory transistors of adjacent NAND memory cells.